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POWERLINK Enhanced Ethernet MAC

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POWERLINK Enhanced Ethernet MAC

The POWERLINK Enhanced Ethernet MAC (PE2MAC) IP Core developed by port is a special MAC controller optimized for POWERLINK. Through several special transmit buffers and the possibility to respond automatically to POWERLINK frames by hardware, extremely short response times are reached.

Overview

The POWERLINK Enhanced Ethernet MAC, PE²MAC, is a parameterizable Ethernet MAC IP core, ideally suited for use in the real time Ethernet networks like Ethernet POWERLINK, EtherNet/IP™ or Modbus TCP. The usage for standard Ethernet applications is still possible.

The PE²MAC core is designed to fulfill the IEEE 802.3 specification and operates at 100Mbps in half- or fullduplex mode. The PE²MAC core interfaces with industry standard PHY devices through a MII interface.

Features

  • FPGA support:
    • Altera Cyclone II/III
    • Xilinx Spartan 3/3E/3A/3AN/3A DSP/6
    • Xilinx Virtex II/II Pro/4/5/6
  • Interfaces for processor connection:
    • Avalon Switch Fabric (Altera NIOS II)
    • PLB v4.6 (Xilinx MicroBlaze)
    • generic SRAM interface
  • MII interface to Ethernet PHY
  • MDIO interface to manage objects in PHY layers (MII Management)
  • 100Mbit / half- and full-duplex operation
  • Configurable packet memory size (up to 64KB)
  • Configurable count of receive buffers (up to 64)
  • Up to 4 transmit buffers
  • 16 independent filters
  • Auto-reply to incoming frames, selected via filters
  • Synchronisation pulse output, selected via filters
  • CRC creation during sending process
  • CRC checking during receive process
  • Diganosis options
  • Frame failure signaling

Description

With FPGAs custom-made, scalable and future-proof solutions open up for the equipment manufacturer. The reusability of IPs, quick time to market and high cost efficiency, are substantial advantages of a FPGA based solution. E.g. a solution with Industrial Ethernet interface, hub logic and processor core can be implemented in one single FPGA. Furthermore the embedded processor can directly be implemented in the FPGA.

port provides a Ethernet Medium Access Controller (MAC) solution specifically for FPGAs tailored to the special needs of POWERLINK, the POWERLINK Enhanced Ethernet MAC (PE²MAC).

To be able to build both, powerful system on chip and independent standalone solutions, the PE²MAC provides different processor interfaces. This includes the Processor Local Bus (PLB) for Xilinx FPGAs and the Avalon Switch Fabric for Altera FPGAs, which allows easy integration with a soft core design. To connect the PE²MAC to an off-chip processor a generic SRAM interface is available.

The connection to the Fast Ethernet PHY device is granted through standard Media Independent Interface (MII).

A clear recognition of every incoming frame is possible due to the 16 independent, free configurable filters, each with a filter depth of 32 Byte. To achieve a flexible configuration, every filter is bitwise configurable by setting a filter value and mask. By filtering all arriving packets, a pre-selection will be done and therefore only those frames that are important for the processing software are stored in packet memory.

The biggest advantage of the PE²MAC is the ability to reply to incoming frames by hardware. This auto-reply feature is used in association with the filters. A filter is selected to generate an auto-reply, everytime this filter matches, the corresponding transmit buffer is then sent automatically. Up to four transmit buffers can be used simultaneously whereby a priorization is done automatically.

The combination of filter and automatic reply mechanism releases the CPU from the task of processing all incoming frames and transmitting a reply if needed. Therefore the response time decreased to the theoretical minimum of the Ethernet interframe gap and the core fulfills the strict response time requirements. The PE²MAC can be used within POWERLINK networks for the lowest cycle times.

Another usefull feature are the synchronisation pulse outputs, which are also used in association whith the filters. If a filter matches, the corresponding sync pulse is generated and the user application and external hardware, i.e. motion control hardware, can be synchronized to this event and therefore to the POWERLINK cycle.

The configurable packet memory has a dynamic, free-shareable address range where input and output packets are stored. Additionally the packet memory can be splitted to seperate receive and transmit packet memory. Access to these packets is granted through descriptors, which contain the start address and the length of the packet.

A special PE²MAC driver provides an optimal interconnection to port’s POWERLINK Library.

In connection with the POWERLINK-HUB not only a straightforward connection to an POWERLINK network is provided but also a sophisticated solution with technical parameters (short response times, fast reaction to network events) that conforms to the requirements of the POWERLINK standard is available.hen.

Technical Data

Platform

Altera-FPGA

Xilinx-FPGA

CPU-Interface

Avalon 
SRAM

PLB 
SRAM

Ressources

2100 LEs 
12 M9Ks

1000 Slices 
6 BRAMs

Operation mode

100MBit

100MBit

PHY interface

MII

MII

Ordering Information

  • 1712/01 POWERLINK Enhanced Ethernet MAC in VHDL for XILINX-FPGAs with PLB-Interface
  • 1712/02 POWERLINK Enhanced Ethernet MAC in VHDL for XILINX-FPGAs with SRAM-Interface
  • 1712/21 POWERLINK Enhanced Ethernet MAC in VHDL for ALTERA-FPGAs with Avalon-Interface
  • 1712/22 POWERLINK Enhanced Ethernet MAC in VHDL for ALTERA-FPGAs with SRAM-Interface

Datasheets

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